1. Field of the Invention
The present invention relates to a method of fabricating a thin film transistor liquid crystal display(TFT-LCD), and more particularly, to a method of fabricating a thin film transistor liquid crystal display to prevent the Mentsuki Effect.
2. Description of the Prior Art
Due to continued development and advancement in electrical technology, the range of application as well as the demand for flat panel displays is ever increasing. A liquid crystal display (LCD) is one type of flat panel display and is employed extensively in small-scale products, such as sphygmomanometer, to various portable electronic devices such as PDAs and notebooks, to such an extent as the commercial big panel display.
At present, the LCD device is primarily composed of a thin film transistor (TFT) with a matrix structure to drive liquid-crystal-pixels so as to generate color-rich graphics. The conventional TFT-LCD includes a transparent substrate having a matrix of thin film transistors, pixel electrodes, scan lines, signal lines, a color filter and liquid-crystal materials between the transparent substrate and the color filter. Since TFT-LCD has the advantages of lightweight, low energy consumption, and free of radiation emission, the TFT-LCD is extensively applied to informational products and has a great potential for the future.
Please refer to FIG. 1 of cross-sectional diagrams of fabricating a single TFT-LCD devicedevice 10 according to the prior art. The prior art technology utilizes the photo-etching-processes(PEP) seven times to form the TFT-LCD device 10 on a transparent glass substrate 11 of a twist-nematic(TN) TFT-LCD 10 system. Only the thin film transistor, the pixel electrode, the scan line, the signal line, the pad and a portion of crossing over of the scan line and the signal line are shown in FIG. 1.
As shown in FIG. 1A, the glass substrate 11 comprises at least one transistor area 210 for forming a thin film transistor(TFT), at least one pad area 220 for forming a pad electrode, and at least one cross over region 230 of scan lines and signal lines. In the prior art method, a first metal layer (not shown) is deposited on the surface of the glass substrate 11, then a first photo-etching-process(PEP-1) is performed to form a gate electrode 12 in the transistor area 210, a pad electrode 14 in the pad area 220, and a scan line 16 passing through the cross over region 230. The gate electrode 12 is connected to another scan line (not shown) on the surface of the glass substrate 11.
As shown in FIG. 1B, after the PEP-1, a first isolation layer 18, a second isolation layer 22, a semiconductor layer 24 and an etching stop layer (not shown) are deposited on the glass substrate 11. Then, a second photo-etching-process (PEP-2) is performed to form an etching stop layer 26 above the gate electrode 12, and other portions of the etching stop layer are totally removed. The semiconductor layer 24 is composed of polysilicon or amorphous silicon; the etching stop layer 26 is made of silicon nitride to prevent the semiconductor layer 24 from erosion in subsequent etching process.
As shown in FIG. 1C, a doped silicon conductive layer 28 is deposited on the semiconductor layer 24 and the etching stop layer 26. Then, a third photo-etching-process(PEP-3) is performed to pattern the doped silicon conductive layer 28, the semiconductor layer 24 and the second isolation layer 22 and remove the doped silicon conductive layer 28, the semiconductor layer 24 and the second isolation layer 22 positioned (a) except the transistor area 210 and (b) except the cross over region 230 for forming a signal line pattern to act as a bottom isolation layer of the subsequent signal line (not shown).
As shown in FIG. 1D, a transparent conductive layer (not shown) is formed on the doped silicon conductive layer 28 and the first isolation layer 18. Then, a fourth photo-etching-process(PEP-4) is performed for forming a transparent conductive layer 32 on the signal line pattern to act as an auxiliary signal line 32, and two pixel electrodes 34 are formed each side of the auxiliary signal line 32 on the first isolation layer 18.
As shown in FIG. 1E, a fifth photo-etching-process(PEP-5) is performed to form an opening in the first isolation layer 18 so as to expose the pad electrode 14 in the opening. Further, as shown in FIG. 1F, a second metal layer (not shown) is deposited over the glass substrate 11. Then, a sixth photo-etching-process(PEP-6) is performed to form a main signal line above the auxiliary signal line 32, and a pad signal line 39 in the pad area 220. The second metal layer 38 is electrically connected to the pixel electrode 34. Another etching process is performed to form an opening in the second metal layer 38 so as to expose the etching stop layer 26 in the opening, therefore, the thin film transistor(TFT) 42 is formed.
Finally, as shown in FIG. 1G, a passivation layer 44 is deposited over the glass substrate 11. Then, a seventh photo-etching-process(PEP-7) is performed to remove the passivation layer 44 positioned (a) above the opening of the pad area 220 and (b) on the surface of the pixel electrode 34, thus portions of the pad signal line 39 and the pixel electrode 34 are exposed.
In summary, the prior art method of fabricating a signal line 36 provides a glass substrate 11, followed by forming a first isolation layer 18 and a second isolation layer (not shown in FIG. 2) on the glass substrate 11. After some photo etching processes, a patterned semiconductor layer 24 and a patterned doped silicon conductive layer 28 are formed over the glass substrate 11 and a signal line is patterned. Afterwards, a transparent conductive layer 32 is patterned on the signal line pattern to act as an auxiliary signal line. Finally, a second metal layer 38 is formed on the transparent conductive layer 32 to act as a main signal line, and the overlapped main signal line and the auxiliary signal line form a signal line 36.
However as shown in FIG. 2, the semiconductor layer 24 and the doped silicon conductive layer 28 are patterned by a same photo mask, and the transparent conductive layer 32 and the second metal layer 38 are patterned by another photo mask. Therefore, after two photo-etching-processes, misalignments and etching errors will be formed. In one liquid crystal display with millions of pixels, this misalignment or overetching phenomena happened frequently. The distance between the signal line 36 and each side of the pixel electrode 34 is defined as xcex40. Actually, after the etching process, the distances between the signal line 36 and each side of the pixel electrode 34 varies between xcex41 and xcex42 due to the misalignment of the process. When the main signal line 38 is formed in the subsequent process, the distances between the signal line 36 and each side of the pixel electrode 34 become xcex43 and xcex44 due to the misalignment of the PEP. These misalignment errors are shown in FIG. 3 of a top view diagram.
When the distances between the signal lines 36 and each side of the pixel electrodes 34 are unequal(xcex43xe2x89xa0xcex44) or exceed a tolerance, the LCD panel would have a bright lines problem, namely the Mentsuki Effect. Therefore, it is important to avoid the problem mentioned above.
It is therefore an object of the present invention to provide a method of fabricating a thin film transistor liquid crystal display(TFT-LCD). The method is used to simplify the process and prevent the Mentsuki Effect of the thin film transistor liquid crystal display.
The present invention provides a method of fabricating a thin film transistor liquid crystal display(TFT-LCD). A TFT-LCD is fabricated on a substrate comprising at least one transistor area for forming a thin film transistor and at least one cross over region of a scan line and a signal line. First, a gate electrode in the transistor area and the scan line passing through the cross over region are formed on the substrate, and both are composed of a first metal layer. Then, a first isolation layer, a second isolation layer and a semiconductor layer are formed to cover the surface of the gate electrode and the scan line. An etching stop layer positioned above the gate electrode is formed on the semiconductor layer. Further, a doped silicon conductive layer is formed on the semiconductor layer and the etching stop layer. The doped silicon conductive layer, the semiconductor layer, and the second isolation layer positioned (a) except the transistor area and (b) except the cross over region are removed. Afterwards, a transparent conductive layer is formed over the substrate, then patterning the transparent conductive layer to form at least one auxiliary signal line passing through the cross over region and at least one pixel electrode on the surface of the substrate. A second metal layer is patterned to form a main signal line on the surface of the auxiliary signal line. An opening is formed in the second metal layer above the etching stop layer to expose the etching stop layer for forming the thin film transistor. The doped silicon conductive layer, the semiconductor layer, the second isolation layer and the first isolation layer are retained on the cross over region where the auxiliary signal line and the scan line pass through. The semiconductor layer, the doped silicon conductive layer and the second layer under the auxiliary signal line except the cross over region are entirely removed.
Since none of the doped silicon conductive layer and the semiconductor layer is formed under the signal line, the errors of the photo etching process are easily controlled. The distances between the signal line and each side of the pixel electrode are equal; therefore the Mentsuki Effect of the conventional liquid crystal display can be solved to prevent bright line defects. However, the second isolation layer, the semiconductor layer and the doped silicon conductive layer are retained in the cross over region to prevent the scan line, the bus signal line or the main signal line from shortening.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.